ACPI support in Coreboot

This is a great issue. I have put a lot energy into this. Now porting ACPI to SB700 is quite easy based on SB600 code. But I have the feeling that I have already forgot something. So I am gonna have to submit a new post to record the whole procedure.

What is Power Management? It is, adding some feature to make your system have the required performance and comsume the least power. Let's skip the boring history and cut to the chase, ACPI. We can go to ACPI spec. That is a whole picture. The goal of this post is to record some useful information in case that I would forgot.

ACPI set up a detailed profile of the whole system. It is provided by BIOS and used by OS. It is put in memory and OS probe it. ACPI uses tables to describe system information. Please go to ACPI spec "ACPI Software Programming Model". You can find the detailed table architecture of ACPI.

The Root table is point by RSDP, from which we can trace all the tables. Of all the tables, 2 are the most important, FADT and DSDT.

1. FADT has the ACPI hardware registers. ACPI hardware registers are defined in spec "ACPI Hardware Specification". They are often located in SB chipset. BIOS should allocate the IO spaces to them and write the IO address in FADT. So the OS can find them.

2. DSDT has the ASL code which describe the system.

(to be continue ...)

tip: (That is why I write this post)
1. Change the frequency of CPU.
orignal information comes from linux kernel Documatation.
linux-2.6.xx/Documentation/cpu-freq/user-guide.txt
All the cpufreq interface is located in
/sys/devices/system/cpu/cpu0/cpufreq/

2. Make the system powerdown or sleep.
bash> poweroff #power down the system.
bash> echo "standby" > /sys/power/state # S1
bash> echo "mem" > /sys/power/state #S3
bash> echo "disk" > /sys/power/state #S4

3. See the temperature of the CPU.
cat /proc/acpi/thermal_zone/XXXX/temperature.

4. See the interrupt infomation.
cat /proc/interrupts

Coreboot - Southbridge 1

I dont know why the SB1 and SB2 are still seperated. That's the way it is and we have to accepted.
For me, it is better to describe it with an example, RS690. It used to be a ATI chipset. Now the ATI has been emerged into AMD. So it is AMD chipset now, located in src/southbridge/amd/rs690. The vendor ID in this chip is still ATI instead of AMD. Relax, AMD has 2 vendor. It is allowable, isn't it?

The Job on RS690 involves only one thing, PCIe. What we have to is to make every PCIe slot work and work in a mode you told them.

Coreboot - SuperIO

The whole coreboot is devided into 4 main part.
1. CPU and Northbridge.
We put these 2 things together because they usually are embedded together.
2. Southbridge 1
3. Southbridge 2
SB1 is connected to Northbridge and SB2 is connected to SB1. Taking dbm690t as an example, SB1 is RS690 and SB2 is SB600.
4. SuperIO.
The SuperIO is connected to SB2. It has the feature which is back compatible to legacy devices, such as PS/2 keyboard and mouse, serial port.
I am going to make a detailed introduction helping people to develop a coreboot based on a given specific board.

Let's start now.
1. SuperIO
I introduce the SuperIO first because it is easiest. And, coreboot need the serial port to work at a very early stage. Coreboot tries to do least work before serial port can work. After the serial port works, we can debug the coreboot by print message to serial.
The superIO is accessed by io port 0x2E and 0x2F. 0x2E is index port, 0x2F is date port. The SuperIO chip always has several logical modules. We set the LDN by index 7 then the
feature is selected.
Select LDN:
outb(0x2E, 7);
outb(0x2F, LDN);
The following action is based on the selected LDN.
outb(0x2E, 0x30);
outb(0x2F, 0x01); /* Enable the logical device */

outb(0x2E, 0x60);
outb(0x2F, MSB);
outb(0x2E, 0x61);
outb(0x2F, LSB); /* set the address used by this device. */
Afterwards, we can access the logical devices by the address which is got by combining the MSB and LSB.
Actually almost all the SuperIO chip is based on the above code. It it not difficult, is it?
After early stage, we need to put the SuperIO into our whole device map. That is done by superio.c. The resources are allocated based on tradional rules. The serial port uses 0x3F8-0x3FF, the keyboard uses 0x60 and 0x64. The OS can also uses the IO port to access the devices and don't have to know the existence of SuperIO chips.
There are several manufactures which provide SuperIO silicon. They are located in directory of superio. Each of them has several types of chips. Actually the chips from one vendor are almost the same. They can use the exact same code. But we have to put them into different folders because we need to define it in mainboard configuation file. When some one modify the code in one folder, the other chips are also need to modified. But no one will do it because that chip has nothing to him. He is reluctant to do it. This need to be resolved.
After the SuperIO works, we need to know how we can make the devices on it also work. The code for PS/2 keyboard and mouse, serial port are almost the same. We dont have to make a new patch for each new SuperIO chip. Relax, they are not difficult at all. Go to src/pc80 and find out what you want.

Debuging Shiner(780/700)

I am now debuging RS780/SB700. Even though we are working for AMD, we can not get a board. I wish I can get something done before I have return the board.

Later I wish I have time to post a blog about how to port coreboot to a given board.